As is known, Monolithic Microwave Integrated Circuits (MMICs) based on PIN diodes are widely used for manufacturing commutators, attenuators, frequency modulators, phase modulators, power limiters etc.
In general, according to the known art, a vertical PIN diode is made starting from a wafer of silicon (Si) or gallium arsenide (GaAs) or indium phosphide (InP) on which a layer of N-type doped semiconductor material, a layer of intrinsic semiconductor material I and a layer of P-type doped semiconductor material are deposited with an epitaxial growth technique, with the layer of intrinsic semiconductor material I interposed between the layer of N-type doped semiconductor material and the layer of P-type doped semiconductor material.
In particular, FIGS. 1-3 schematically show the cross-section of a vertical PIN diode manufactured according to a known manufacturing process. In detail, in FIG. 1 reference numeral 10 indicates, as a whole, a vertical PIN diode comprising an epitaxial wafer made by means of the epitaxial growth technique, by depositing a sequence of layers on a wafer of semiconductor material, of GaAs for example, these layers comprising from the bottom to the top:
a semi-insulating substrate 11;
an N+-type layer 12 formed on the semi-insulating substrate 11;
an intrinsic layer I 13 formed on the N+-type layer 12; and
a P+-type layer 14 formed on the intrinsic layer I 13.
Furthermore, always with reference to FIG. 1, in order to form an anode contact of the vertical PIN diode 10, an anode metallization 15 is formed on a portion of the P+-type layer 14 defining an anode region 14a. After having made the anode contact, a first trench is formed in the P+-type layer 14 and in the intrinsic layer I 13 so as to expose the surface of portions of the N+-type layer 12. In particular, the first trench is formed by a first dry etching self-aligned with the anode metallization 15.
In detail, the first dry etching, even if an anisotropic etching, i.e. etching that mainly acts in a direction perpendicular to the upper surface of the epitaxial wafer, in any case also removes portions of the anode region 14a and of the intrinsic layer I 13 beneath the anode region 14a, despite them being protected by the anode metallization 15, so that, at the end of said first dry etching, portions of the anode metallization 15 extend laterally from the residual anode region 14a and from the residual intrinsic layer I 13 not removed by the first dry etching for an extent called Under-Cut (UC). In addition, after performing the first dry etching, in order to form a cathode contact of the vertical PIN diode 10, a cathode metallization is formed on a first exposed portion of the N+-type layer 12 defining a cathode region.
Lastly, in order to electrically insulate the vertical PIN diode 10 from other components created in the same MMIC, such as other PIN diodes and/or passive components such as capacitors, inductors and resistances, a second trench is formed in exposed portions of the conductive layers so as to expose portions of the underlying layers made with non-conductive semiconductor material.
In particular, the second trench is formed in a second exposed portion of the N+-type layer 12, distinct from the cathode region, so as to expose the surface of underlying portions of the semi-insulating substrate 11. In detail, the second trench is formed by a second dry etching. Consequently, with reference to FIG. 2, after having made the second trench, the vertical PIN diode 10 comprises, from the bottom to the top:
the semi-insulating substrate 11;
the N+-type layer 12 that partially covers the semi-insulating substrate 11 leaving exposed a portion of said semi-insulating substrate 11 that extends laterally from the N+-type layer 12;
the residual intrinsic layer I 13 not removed by the first dry etching that partially covers the N+-type layer 12 leaving exposed portions of said N+-type layer 12 that extend laterally from the residual intrinsic layer I 13;
a cathode metallization 16 formed on a exposed portion of the N+-type layer 12 defining the cathode region;
the residual anode region 14a not removed by the first dry etching that completely covers the residual intrinsic layer I 13; and
the anode metallization 15 that completely covers the residual anode region 14a and that comprises portions that extend laterally from the residual anode region 14a for an UC extent.
Furthermore, with reference to FIG. 3, in order to make an anode contact connection and a cathode contact connection, a first high-thickness metal air-bridge 17 is made in correspondence to the anode metallization 15 and a second high-thickness metal air-bridge 18 is made in correspondence to the cathode metallization 16.
The Applicant has noted, however, that the known manufacturing processes for vertical PIN diodes have several technical drawbacks.
In particular, the Applicant has noted that the first dry etching, especially when it has mainly anisotropic characteristics, i.e. when it mainly acts in direction perpendicular to the upper surface of the epitaxial wafer, induces mechanical damage and/or a residual deposit, particularly on the walls orthogonal to the etching direction, which causes damage on the surfaces of the semiconductor exposed to the plasma, in particular on those of the intrinsic layer I 13, and frequently cause high leakage currents when the vertical PIN diode is cut off, or rather when it is not polarized or inversely polarized, causing the following problems:
1) the conduction of current when the diode is cut off induces loss of insulation, at both low and high radio frequency signals (RF), also inducing a source of noise in the circuit where it is applied;
2) the flow of current through the diode, especially when it is inversely polarized at a high voltage, entails energy consumption by the diode, at the expense of the energy efficiency of the circuit itself; and
3) the currents induced by these surface effects can, in turn, lead to the creation of further defects, thereby inducing degradation that can affect the reliability of the circuit.
Moreover, when the reactive plasma used during the etching process is in the chemical-physical conditions to induce less damage to the semiconductor crystal it come into contact with, and which generally impose limits on its minimum pressure and its maximum acceleration energy, etching has a greater isotropic action, i.e. it also has a weak etching action on the semiconductor even in directions not parallel to that perpendicular to the upper surface of the epitaxial wafer. For this reason, namely in conditions of isotropic or partially isotropic etching, the first dry etching, in any case, also removes portions of the anode region 14a beneath the anode metallization 15, thereby causing lateral shrinkage of the area where the anode contact is formed, and this poses practical limitations in making diodes with low parasitic capacitances and resistances, where the limited minimum lateral dimensions associated with the high thicknesses of the intrinsic layer I 13 render the use of low-damage etching processes more critical. This problem is further exalted in the case where the anode contact connection is made through a high-thickness metal air-bridge, as in the situation shown in FIG. 3, due to the difficulties associated with the minimum lithographic resolution for making bridges with minimal contact areas.
Thus, based on what has just been described, the Applicant has reached the conclusion that the known manufacturing processes for vertical PIN diodes do not permit having accurate control over the width of the anode contact.
Known manufacturing processes for vertical PIN diodes that have the above-stated drawbacks are described in Seymour D. J. et al., “MONOLITHIC MBE GaAs PIN DIODE LIMITER”, IEEE 1987 Microwave and Millimeter-Wave Monolithic Circuits Symposium, Digest of papers (Cat. No. 87CH2478-6) IEEE New York, N.Y., USA, 1987, pages 35-37, and in U.S. Pat. No. 5,213,994.